FIG. 7 shows one of the conventional timing-signal delay equipment where an input timing signal Q1 is supplied to a logic gate 1 whose output is connected to a cascade circuit G composed of n delay elements D.sub.1 -D.sub.n connected serially, each of which is of the same structure comprising a resistor R and a variable capacitor C as shown. The binary coded error information E, which is defined to represent the difference between a predetermined set-up value of delay time and the delay time of an output timing signal Q2 actually obtained at the cascade circuit G to its input timing signal Q1, makes a D/A converter B generate an analog control signal that controls the capacitance of each variable capacitor in delay elements D.sub.1 -D.sub.n so that the delay time of output timing signal Q2 to its input timing signal Q1 becomes almost equal to said set-up value.
FIG. 8 shows another conventional timing-signal delay equipment which has a cascade circuit G composed of a waveform converter 11 which converts an input timing signal Q1 to a triangular waveform, whose output is connected to a threshold gate circuit 12. A D/A converter B with error information E of the same definition as before at its input, provides an analog control signal that controls the threshold level of the threshold gate circuit 12 so that the delay time of an output timing signal Q2 obtained at the cascade circuit G to its input timing signal Q1 becomes almost equal to said set-up value.